A Parallelized Real-time Image Convolution Algorithm with Systemverilog
Open Access
Author:
Yu, Brian S
Area of Honors:
Electrical Engineering
Degree:
Bachelor of Science
Document Type:
Thesis
Thesis Supervisors:
Dr. John Phillip Sustersic Jr., Thesis Supervisor Jeffrey Scott Mayer, Thesis Honors Advisor
Keywords:
image processing parallel processing systemverilog fpga difference of gaussians
Abstract:
Visual salience is a perceptual quality by which an item stands out from its neighbors, grabbing the attention of a viewer. A computer model that can detect salient objects quickly has many applications in the field of computer vision. However, a major limitation of implementing salience detection in computers is the computational power required to process the large amount of data at real-time speeds. In this paper, the implementation of a parallelized Difference of Gaussian pyramid convolution algorithm to be used on a cluster of high-performance FPGA is designed and characterized. Written in SystemVerilog, emphasis is made on parallelizability, design modularity, and parameterization. Under this design, each level of the Difference of Gaussians pyramid can be calculated as quickly as pixels come in, minus some initialization overhead. Performance is affected primarily by the number of pixels to be processed, and the number of levels in the pyramid has little impact. In this highly parallelized design, an FPGA implementation would be effective for real-time processing on high-resolution image inputs.
