This thesis explores the circuit implications of ferroelectric transistors with a focus on the effects of ferroelectric material thickness. Ferroelectric transistors have a thin layer of ferroelectric material deposited on the gate of the device. This material causes the behavior of the device to change due to its negative capacitance. While there are many variables which contribute to this effect, with all other variables fixed, the material thickness can be used to explore some of the actions of the ferroelectric transistors.
This thesis shows transistor characteristics of the ferroelectric transistors mapped with respect to the ferroelectric material thickness. A ring oscillator is also used to explore the energy and delay of the ferroelectric transistors. Also, 6T SRAM cells are explored with respect to ferroelectric transistors to understand the implications of their use within SRAM cells. Ferroelectric transistors are found to be useful in low power systems to mitigate some of the issues that traditional MOSFETs encounter when in the same setting.
