The capabilities and implementation of simple hardware based neural networks are explored within
the context of two unique pattern classification tasks; handwritten digit classification and removal of
eyeblink and other high amplitude artifacts from raw electroencephalogram (EEG) data. Regular neural
networks are each constructed with accuracies of 78.68% and 87.20% respectively. Next, I simulate a
physically realized neural network hardware architecture. This utilizes NAND flash memory floating gate
transistors as a memory source for weight matrix storage. The NAND devices are arranged in a crossbar
array which allows for necessary matrix operations to occur. The individual NAND memory devices are
simulated using threshold shift modifications to the Virtual Source Model.
