Enhancing Capability Deployment Efficiency through Stack Safety Analysis

Open Access
- Author:
- Kurose, Yuh
- Area of Honors:
- Computer Engineering
- Degree:
- Bachelor of Science
- Document Type:
- Thesis
- Thesis Supervisors:
- John Morgan Sampson, Thesis Supervisor
John Morgan Sampson, Thesis Honors Advisor
Vijaykrishnan Narayanan, Faculty Reader - Keywords:
- Memory Security
C/C++
LLVM
Static Analysis
Stack Safety - Abstract:
- As the world’s dependence on technology continues to increase, effective memory protection mechanisms are critical for safeguarding computer systems. Traditional methods, while helpful, can often fall short in addressing complex security challenges, increase program complexity, or lack scalability. To address these gaps, the University of Cambridge and SRI International developed the Capability Hardware Enhanced RISC Instructions (CHERI) architecture, enhancing memory security through a fine-grained, pure capability-based addressing system. These capabilities work similarly to a traditional pointer but also possess metadata regarding size and bounds, significantly mitigating risks of unauthorized access to memory and allowing for fine-grained, hardware-based memory security. A platform leveraging CHERI’s research is the ARM Morello machine, a capability hardware enhanced ARM architecture. Despite its robust security, there remains an opportunity to optimize its implementation for improved efficiency via an improved analysis. This thesis proposes an enhancement of the ARM Morello’s capability deployment system by integrating the DataGuard framework’s stack analysis abilities. DataGuard, which utilizes an extensive static analysis to offer a higher level of accuracy to determine safe and unsafe memory accesses and determine safe and unsafe stack objects, can be integrated with Morello’s existing capability deployment to optimize bounds setting, reducing computational overhead while maintaining high security standards. The function-safety based system had a modest, yet consistent improvement of 0.56% in runtime over the standard CHERI-LLVM in the SPECint2006 benchmarks conducted, without sacrificing security.