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Author:

Yu, Brian S

Title:

A Parallelized Real-time Image Convolution Algorithm with Systemverilog

Area of Honors:

Electrical Engineering

Keywords:

image processing
parallel processing
systemverilog
fpga
difference of gaussians

File:

Download thesis_final.pdf

Thesis Supervisors:

Dr. John Phillip Sustersic Jr., Thesis Supervisor
Jeffrey Scott Mayer, Thesis Honors Advisor